1. Field of the Invention
The present invention relates to failure analysis techniques for integrated circuits (ICs), and in particular, to systems and methods for detecting locations of defective electrical connections within ICs.
2. Description of the Related Art
As ICs have become increasingly complex and capable of more functions, in terms of both quantities and varieties, the electrical interconnections between the various devices and functional blocks increasingly have become of more significant concern. Such electrical interconnections, which are necessarily resistive (albeit ideally with small resistances), include interconnections between the various layers of semiconductor material(s) and metal within an IC. These interlayer connections include contacts and vias which are necessarily fabricated in parts as the successive layers of the IC are deposited or otherwise developed.
There are many failure mechanisms for these vias, so with increasing numbers of vias in an IC it is increasingly important that failures be diagnosed, located and resolved as quickly as possible. Many conventional techniques have been used to test for hot spots on the surface of an IC, including infrared optical microscopy, light emission microscopy, transistor logic state mapping, induced thermal effect imaging and scanning laser microscopy. (A discussion of scanning laser microscopy can be found in Cole Jr. et al., “Resistive Interconnection Localization”, Proceeding from the 27th International Symposium for Testing and Failure Analysis, November 11-15, 2001, Santa Clara, Calif., the contents of which are incorporated herein by reference.)
Once these hot spots are found, the x and y coordinates are noted and de-processing of the IC is begun. Since there are multiple successive layers on the IC, the de-processing must be performed layer by layer from the top to the bottom in order to determine where the hot spots originate. Generally, a Reaction of Ion Etching (RIE) system is used to remove each layer of the IC, following which the IC is then placed under a Scanning Electron Microscope (SEM) for the failure analysis (FA) engineers to find the defect. If no defect is found, the next layer is removed. Both RIE and SEM must be operated in vacuum environments, thereby requiring a significant amount of time due to the venting and pumping required. As a result, much time is consumed in locating the defect, especially with an IC containing many layers. Further, the actual defect can sometimes be missed or damaged such that its failure mechanism cannot be determined.